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A24 - A Programmer's Guide for Modern High-Performance Computing

From: December 10 to 14, 2018 Registration is Closed


A24 – A Programmer's Guide for Modern High-Performance Computing Architectures

High-performance computing has seen a lot of interesting advances in the last decade, in both architectures and programming models. In terms of architectures, we have seen massive parallelism and various kinds of accelerators appearing with the promise of TeraFLOPs of performance. More and more application fields are tempted by the promise of many-fold performance gains, and willing to design and implement HPC solutions for their use-cases.

Despite the enthusiasm, programming these novel HPC architectures is hard work. In fact, achieving the promised level of performance often requires suitable workloads, algorithm re-writing, multilayered parallelization, multi-grain concurrency, and aggressive optimization and tuning. None of these challenges should be good reasons to give up, but reasons enough to get to know more about programming these novel HPC architectures, while understanding their strong points, their limitation, and ultimately their "down-to-Earth" performance.

This course - A Programmer's Guide for Modern High-Performance Computing Architectures - is designed to respond to this need of understanding and being able to program novel HPC architectures. Specifically, the course covers three types of HPC architectures – multi-core processors, GPU accelerators, and FPGA accelerators -, and the programming models and techniques used for them. The intended outcome of the course is an understanding of the issues and problems in using these types of processors, the ability to analyze and predict the performance to be expected from them in cases of real-applications, and practical knowledge in choosing the right machine and programming model for a given application.

Schedule

The course is scheduled between December 10-14, 2018. It has 4.5 days of combined theoretical lectures and hands-on lab-work. The daily schedule is split in two parts: morning lectures from 10:00 to 13:00, and afternoon practical work, from 14:00 to 17:00.

Monday (10-17) - room 320.D D0.01 (by Ana Varbanescu) Introduction : machines, parallel algorithms and applications, performance metrics

Tuesday (10-17) - room 320.D D1.00 (by Ben van Werkhoven) GPU day Wednesday (9-13) - room 320.C CK.07 (by Giulio Stramondo and Ana Varbanescu) FPGA day

Thursday (10-13) - room 320.B B2.07 (by Clemens Grelck) (13-17) - room 320.B B2.04 (by Clemens Grelck) Multi-core day & OpenMP

Friday (10-17) - room 320.C CK.06 (by Alexandru Iosup) Large scale systems & cloud computing day.

 

The course will be held at the UvA Campus (all the rooms are at Roeterseiland)

http://campus.uva.nl/en/roeterseiland/roeterseiland-campus.html

 

 

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